Citrini analyst Jukan said on X that, according to Odaily, South Korea’s ETNews reported TSMC is building a supply chain for CoPoS materials, components, and equipment, with a goal of reaching mass production next year.
The post also described panel-level packaging (PLP) as a technology that packages diced chips on rectangular panels. It said PLP can reduce edge-area waste compared with wafer-level packaging (WLP), which uses circular wafers.
Using a standard 600×600 mm rectangular panel as an example, the post said chip output is about five to six times that of a mainstream 300 mm (12-inch) wafer.
AI TRENDS | Citrini Analyst Jukan Says TSMC Is Building a CoPoS Supply Chain for Mass Production Next Year
2026-06-15 05:24:26
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